An Inductorless 20-Gb/s CDR With High Jitter Tolerance

A full-rate clock and data recovery loop employs a three-stage ring voltage-controlled oscillator, a master-slave passive sampler as both a phase detector and a filter, and a new flip-flop to achieve a loop bandwidth of 170 MHz. Implemented in 45-nm CMOS technology, the circuit occupies an area of 14 μm × 26 μm and exhibits a jitter tolerance of 2 TiI at 5 MHz and a recovered clock jitter of 459 fs with 2
³¹
- 1 pseudorandom bit sequence.