Cost-Effective and Time-Efficient Failure Analysis Method for Yield Enhancement Utilizing Picked Sawn Wafer

Electrical and physical failure analyses have played a key role in the yield enhancement of large-scale integrated circuits. However, the growing cost of product wafers has progressively hindered their use for analysis, depending on the shrinkage of device dimensions. To overcome these difficulties, we propose a new analytical style that uses the remaining dies on a sawn wafer after all the good dies have been picked and taken for assembly. We call the resulting structure a “skeleton-wafer”. In the present study, we have developed a testing system that can handle a skeleton-wafer in the same manner as a conventional wafer. Basically, skeleton-wafer testing is performed at room temperature, given that commonly used dicing tapes have low heat-resistance. We have also developed a sophisticated method that enables analytical testing on the remaining dies at high temperature. A case example achieves high throughput and good contact characteristics, enabling the developed system to be of practical use in high-volume electrical failure analysis. We illustrate how our analytical testing system has improved cost-effectiveness and time-efficiency in yield enhancement activity.