Throughput Optimization of Fast Processing Tools Using a Dispatching Algorithm

Throughput of certain fast processing tool sets in a semiconductor Fab is sometimes constrained by limitations of FOUP delivery system. The delivery system not being able to keep up with the tools result in a certain throughput loss. This throughput loss can be mitigated by staging the WIP close to tools. However, WIP staging has its limitations. This study presents a methodology to overcome these limitations by staging the WIP just in time for dispatching.