Hysteresis Dynamics in Double-Gated n-Type WSe2 FETs With High-k Top Gate Dielectric

We propose double-gated n-type WSe
₂
FETs with low leakage, low hysteresis top gate high-k dielectric stack. The top gate dielectric layer is deposited by HfO
₂
ALD on an Al
₂
O
₃
seed layer obtained from the evaporation and oxidation by air exposure of a 1.5 nm Al layer. When operated under back gate control, the fabricated WSe
₂
FETs behave as n-type enhancement transistors with ON/OFF current ratios exceeding 6 orders of magnitude and a ON current close to 1 μA/μm at a drain bias of 100 mV. An applied negative top gate bias determines a much steeper turn-on of the back gated transfer characteristic and a reduction of the observed hysteresis. Top gate devices behave as n-type depletion FETs, reaching a ION/IOFF ratio larger than 10
⁶
under positive bias applied to the back gate. The electron mobility, extracted using the Y-function method, was estimated to be 22.15 cm
²
V
^-1
s
^-1
under a drain bias of 1 mV. We characterize the hysteresis dynamics in our devices, demonstrating a substantial improvement with respect to comparable top gated MoS
₂
FETs.