Trade-offs and Other Challenges in CMOS Implementation of Parallel FIR Filters

The paper presents methods of implementing finite impulse response (FIR) filters in hardware. Considering their functioning, FIR filters require only simple arithmetic operations such as multiplication, addition and shifting of signal samples in the delay line. In the case of their implementation as a device in which parallel processing of signals is assumed, one of the main challenges is an efficient implementation of the block of filter coefficients. This applies in particular to high order, N filters and a relatively high resolution (in bits) of the processed signals and filter coefficients. When the objective is to reach a high filter selectivity, understood as the attenuation in the stop band and the steepness in the transient band of the frequency response, the filter coefficients usually also require high resolutions. In the presented work we perform an analysis of trade-offs between such parameters as data rate, occupied chip area (number of transistors), simplicity of the control block as well as energy consumption. We investigate possible approaches to the implementation of such filters, particularly in terms of the complexity of the block of coefficients. One of the key possibilities is the use of at least partially asynchronous signal processing, which has a significant impact on the complexity of the circuit structure and data rates.