A New Approach to Optimize the Defuzzification Unit of Fuzzy Systems

Fuzzy systems have numerous advantages in mathematical and logical operations, and that's why they are being used in parallel with digital processors to handle some of their mathematical functionalities. The focus of this paper is on the optimization of the output side of the system, which is defuzzifier unit. The defuzzifier transforms the fuzzy data of the system to crisp data and can be implemented using different structures. The structure used in this paper, consists of three types of blocks: adders, multipliers and dividers. Since the system works by the side of a digital processor, an analog to digital converter (ADC) should be added next to the defuzzifier, to convert the crisp output to digital data. Considering the defuzzifier and the ADC as a single unit, it will have four blocks, which occupy a large chip area and consume a huge amount of power. To mitigate these objections, some solutions should be proposed. By designing the circuits in current mode there will be no need for adders and by delegating the role of division to ADC, the divider will be deleted. The proposed circuits are simulated in H-spice and the layouts are drawn in Cadence virtuoso. The simulation results show that power consumption and the chip area of the proposed structure (counting ADC) are 40 mw and 300μm*150μm, the results also prove that the proposed method has better quality factor (QF) compared to former works.