Packaging of a massively parallel signal processor for spaceflight

Concepts for the packaging of a massively parallel signal processor for a radar surveillance satellite are investigated. The signal processor assumed employs 32 custom processor dice arranged as a parallel computer. The significant packaging challenge is interconnection of the various processor dice while maintaining a stringent time-of-flight requirement for the high speed signals. The total number of interconnects for the 32 dice is approximately 12,800 where the high speed interconnect requirement concerns approximately 4800 interconnects. Various packaging and routing strategies are investigated with a statistical comparison of the routes provided.