Analytical modelling and simulation of pseudo-resistive circuit techniques for biomedical applications

Pseudo-resistors (PRs) implemented on-chip have become extremely popular than passive off-chip linear resistors as they serve an effective way to emulate high value of Incremental Resistance (IR). The nonlinear V-I characteristics of PRs and their high sensitivity toward Process Voltage and Temperature (PVT) variations degrades the performance of analog circuits used in biomedical applications. In this work, different PR techniques have been modeled in subthreshold region for calculating IR expression and IR range associated with them. All the simulations and statistical analysis have been performed on 0.18 μm standard CMOS process using BSIM3V3 MOS models. It was found that statistical results and linearity improves when the bulk terminal of the MOS device is either connected to drain or a bias voltage is applied to it. Among all the PR techniques reported in this paper, Scaled Gate Linearization (SGL) emulates IR of the order of 1 TΩ with highest linearity for source to drain voltage (VSD) between -1 to 0.3 V. For SGL, the nominal value of IR (RSD,N), and mean μ, are 999.99 GΩ and 1 TΩ respectively with negligibly small difference between these values. Moreover, the values of standard deviation (σ) and Coefficient of variance (CV=σ/μ) for SGL are too low, i.e. 1.364 MΩ, and 1.36×10
^-6
respectively. The PR techniques reported in this work are anticipated to be used in different analog circuits for numerous biomedical applications.