Design of Low Leakage SRAM Bitcell

CMOS scaling affects to sub-threshold leakage, gate leakage and device variations growth leakage current. Static Random Access Memory (SRAM) cell is engaged the most area of Integrated Circuit (IC). It has been implemented FinFET bitcell, which leakage becomes the significant key factor in SRAM. In addition, proposed to implement 8T SRAM cell using diode connected NMOS/PMOS transistors to reduce leakage current. Different approaches were used for leakage reduction in the proposed circuit. Consequently, leakage power in the SRAM bitcell is reduced and runs better performance. The proposed SRAM bitcell showed an improvement of about 3 times leakage power over the 6T SRAM bitcell. Read and Write access times of the proposed SRAM bitcell increases about 18 %. Power also reduced about 10%. The proposed techniques of leakage reduction have been implemented by using Synopsys Armenia Educational Department's SAED 14 nm technology for FinFET SRAM.