A High-Performance Fully Integrated 900-MHz Passive RFID Tag EPC C1G2 Analog Front End

In this paper, a high performance fully integrated 900 MHz analog front end for UHF RFID tag EPC C1 G2 standard protocol is presented. The proposed analog front end consists of a voltage regulation which consists of an RF to DC converter, voltage regulator circuit which regulated the DC voltage to prefer value (0.5V), ASK modulator/demodulator, a clock generator and a power on reset circuit. To minimize the power consumption of RFID transponder we propose the minimizing of the input voltage of the converter. Proposed regulator is designed under following conditions: RF frequency's 900 MHz, 50 Ω antenna, a sensitivity of -24 dBm and a maximum power consumption of 1 μW. At 0.5 V proposed demodulator can demodulate the minimum input power -24 dBm for a modulation index of 37-100 % with 160 kbps data rates and consumes only12.74 nW. The power consumption and layout of the analog front end proposed in this work are about 1 uW and only 79 μm × 67 μm respectively. The simulation results dawn in 0.18 μm CMOS technology confirm the performance of the proposed analog front-end.