A novel low-power microprocessor architecture

This paper presents a novel microprocessor architecture, that was especially designed to reduce the power dissipation of modern systems-on-a-chip. The applications we aim at with this architecture are ultra-low-power embedded systems like intelligent medical implants or sensorized micro-transponders. We introduce new types of data storage files and hardware supported constant elimination to utilize the mostly local scope of common arithmetic operations for reducing energy. A multi-level instruction-cache scheme together with a cache controller supporting sophisticated opcode preprocessing operations like Huffman decoding decreases the amount of external memory accesses and size. Additionally the width of pointers is significantly reduced by a table-lookup cache-miss concept. Finally a segmented gray-code address counter minimizes the transitions on external buses. All these concepts combine into a completely new type of microprocessor architecture, which is designed to reduce transitions per operation as much as possible.