Graceful Fault-Tolerant On-Chip Spike Routing Algorithm for Mesh-Based Spiking Neural Networks

Hardware implementation of Artificial Spiking Neural-Networks (SNNs) is increasingly used in mission-critical applications, such as control systems, biomedical, and aerospace that demand low failure rates and fault tolerance. Since computation and information in a given SNN/ANN system are distributed, an error in a single neuron, axon/interconnect, or in a synaptic strength affects the whole computation and may degrade the system's operation. This paper proposes a fault-tolerant k-means based multicast routing algorithm (FT-KMCR) to deal with the interconnect (axon) faults in 3D-NoC Mesh-based Spiking Neuromorphic Chips. The proposed algorithm computes a pre-planned multicast tree and backup branches by using k-means clustering and tree-based method. The FT-KMCR was integrated into our 3DNoC-SNN architecture. The system was validated based on RTL-level implementation, while the area and power analysis are performed using 45-nm CMOS technology. From the evaluation results, we find that the proposed fault-tolerant methodology enables the system to sustain correct traffic communication with a fault rate up to 20%, while suffering small performance degradation (17.36% longer latency and 5.49% extra area cost) when compared to the baseline system.