Power integrity Flow for mixed-signal NVM flash IP

Proliferation of IoT and secured applications is driving STMicroelectronics NVM Flash memories requirements toward increasing integration, lower power and faster reading times. Challenges resulting from this trend is addressed through continuous improvements of our mixed-design flows. Regarding power integrity, we are adopting more accurate dynamic voltage drop simulation flow, while keeping reasonable run times. In this presentation, we will review our motivations for improving the power integrity flow. Theoretical approach as well as our improved NVM hierarchical (IP to SOC) Power Integrity (PI) flow will be exposed. Then flow automation and flexibility required in order to fulfill our needs will be discussed as well as the benefits.