Method of Time Sampling Error of Time-Interleaved ADC Based on Statistical Rule

The rapid development of digital technology requires higher Analog Digital Converter (ADC) sampling rates. Single-chip ADC is difficult to meet this require. The Time Interleaved ADC (TIADC) based on ADC parallel sampling can solve this problem and is therefore widely used. However, due to current hardware levels, the sampling interval of the TIADC is non-uniform and there is a time sampling error (TSE). There are currently a number of algorithms that can estimate the TSE, but must work in an environment where the frequency of the input signal is known. This paper improves an existing TSE estimation method that enables parameter estimation with unknown input signal frequencies. The proposed algorithm constructs the relationship between signal variance and TSE. In the implementation process, the TSE estimation value is inverted by statistical signal variance. Simulations show that the normalized TSE estimation error value variance is 0.01.