A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth

This work presents two capacitor mismatch error reduction techniques, sorted-capacitor averaging (SCA) and two-phase averaging (TPA), combined with the finite opamp gain error reduction technique, averaging correlated level shifting (ACLS), in two modes of the proposed ADC. For 20MHz and 15MHz input sampling at 40/30MS/s, the ADC operating in SCA/TPA modes achieves 71.2/74.5dB SNDR with a power consumption of 5.5/5.2mW, yielding Walden and Schreier Figure-of-Merits of 46.3/40.0fJ/conversion-step and 166.8/169.1dB, respectively.