Nanoscale CMOS Implications on Analog/Mixed-Signal Design

AMS design in remaining CMOS nodes is tedious & about managing technology-imposed non-idealities. AMS area scaling 0.8-0.9x per node vs. 0.5x for logic & SRAM. Parasitics a LDEs only get worse, will ultimately limit scaling. Digital-friendly AMS design inspires new performance, power & integration levels. AMS design at inflection towards more automation to reduce design iterations.