A Low Cost 100 MHz 2-Stage PSiP and Evolution to a Co-Packaged/Fully-Integrated Voltage Regulator for SoC Power Delivery

A self-contained power delivery system in a SiP package or co-packaged in an SoC POP for CPU and GPU cell phone application is presented. State of the art performance is achieved utilizing a low-cost high voltage (5 V/1.3 V) process (0.13 μm BCD). This allows either a 2-stage or single-stage combined version on the same die. The path towards fully integrated power supply on SoC chip or co-packaged is described with results. Ongoing methods and options for realizing integrated or co-package inductors are being developed simulated and fabricated with results provided. Initial results of a stage 2, 100 MHz PSiP are also included with fast DVS results (>1 V/μs). Transient response and settling of less than 100 ns, consistent with 10 MHz bandwidth, were also obtained. Advantages of a 0.13 μm process include lower cost per unit area, lower leakage, increased dynamic range, more accurate and lower power references. Performance results are superior to other stage 2 results reported using more advanced CMOS process technology nodes (28 nm and 14 Trigate) and at a lower cost. Evolution to a fully integrated high performance 2stage design is presented with simulated and measured results.