A 2MHz BW Buffer-Embedded Noise-Shaping SAR ADC Achieving 73.8dB SNDR and 87.3dB SFDR

This paper presents a buffer-embedded noise-shaping SAR ADC, which separates the capacitive DAC (CDAC) and the sampling capacitor (C
_S
) placed at the input and output of input buffer. This compensates the nonlinearity of the input buffer and enables C
_S
value to be reduced, thus leading to significant power saving. An energy efficient 2
^nd
-order noise-shaping is realized using passive integrators with the C
_S
and the mismatch of CDAC is mitigated by error shaping techniques. Implemented in a 65 nm CMOS process, the ADC achieved 73.8 dB SNDR, 77 dB DR, and 87.3 dB SFDR in a 2 MHz bandwidth without any calibration. It consumes only 2.13 mW including the input buffer.