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A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure | IEEE Conference Publication | IEEE Xplore

A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure


Abstract:

This paper presents a capacitive-coupled VCO-based sensor readout featuring a hybrid PLL-ΔΣM structure. It leverages phase-locking and PFD array to concurrently perform q...Show More

Abstract:

This paper presents a capacitive-coupled VCO-based sensor readout featuring a hybrid PLL-ΔΣM structure. It leverages phase-locking and PFD array to concurrently perform quantization and DEM, much reducing hardware/power compared to existing VCO-based readouts counting scheme. A low-cost in-cell DWA scheme is presented to enable highly linear tri-level DAC. Fabricated in 40nm CMOS, the prototype readout achieves 78dB SNDR in 10kHz BW, consuming 4.5μW and 0.025mm2 active area. With 172dB Schreier FoM, its efficiency advances state-of-the-art VCO-based readouts by 50×.
Date of Conference: 14-17 April 2019
Date Added to IEEE Xplore: 01 August 2019
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Conference Location: Austin, TX, USA

References

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