A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth

We present a CTΔΣM which uses a virtualground-switched resistor DAC to achieve low distortion by reducing the effects of inter-symbol interference (/S/), and parasitic resistance in the reference path. 1/f noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a 3-stage OTA, and an 8-tap F/R feedback DAC. Fabricated in 180 nm CMOS, the prototype modulator operates at 32 MS/s and achieves 103.5/107.5 dB SNDR/DR in a 250 kHz bandwidth while consuming 24 mW. The Schreier FoM is 173.7 dB.