Performance Analysis of SRAM Cell Designed using MOS and Floating-gate MOS for Ultralow Power Technology

With the enhancement in semiconductor based tools scaling and heightening in transistor density, realization of novel concept of minuscule electronic devices become imperative to design. SRAM being a volatile memory devised as a static Random Access Memory for high speed, low power based appliances having active and standby based benefits. Due to these pros technology is pondering on contracting down. This led to the invention of various low power based protocols showing enlightened gains. FGMOS is an approach deliberating minimal power designs which involves few transistors maintaining large tune ability, compatibility, fan -in, and flexibility. It moves in threshold voltage producing higher speed, controllability and better performance. The proposed paper introduces FGMOS and instigate it in 6T SRAM in 90 NM Technology employing under gpdk 090 (generic process design) kit using Cadence virtuoso and has been evaluated.