Chemical reaction concerns of gate metal with gate dielectric in Ta gate MOS devices: an effect of self-sealing barrier configuration interposed between Ta and SiO/sub 2/

Chemical reaction of gate metal with gate dielectric for Ta gate MOS devices has been experimentally investigated both by electrical and physical measurements: capacitance-voltage (C-V), current-voltage (I-V), transmission electron microscopy (TEM), energy dispersive X-ray (EDX), electron diffraction measurements. In spite of the chemical reaction of Ta with SiO/sub 2/ consuming /spl sim/1-nm-thick in gate oxide, the interface trap densities of /spl sim/2/spl times/10/sup 10/ cm/sup -2/ eV/sup -1/ at midgap and ideal channel mobility characteristics have been observed in the Ta gate MOS devices with 5.5-nm-thick thermal oxide gate dielectric. Considering the experimental data with theoretical calculation based on thermodynamics together, a barrier layer model has been developed for the Ta gate MOS systems. The physical mechanism involved is probably self-sealing barrier layer formation resulting from the chemical reaction kinetics in the free-energy change of Ta-Si-O system.