A novel sub-10 nm transistor

We report on a novel transistor structure which has the special features of (1) precise gate length control through a deposited film thickness; (2) an ultra-thin body for suppression of short channel effects; (3) raised source/drain (S/D) to reduce parasitic resistance; (4) a gate-last process compatible with high-k low temperature dielectrics; and (5) a low thermal budget process. Using this structure, transistors with a 9 nm gate length have been fabricated without the use of advanced lithography. To the authors' knowledge, this is the smallest reported functional NMOS transistor.