Power and Delay Analysis of Junction-Less Double Gate CMOS Inverter in Near and Sub-Threshold Regime

In this paper, a Junction-Less Double Gate MOSFET (JLDG MOSFET) based CMOS inverter circuit is proposed for ultra-low power applications in the near and sub-threshold regime operations. D.C performances like power and delay of the proposed Inverter have been modeled analytically and analyzed in depth. JLDG MOSFET has promising features to reduce the short channel effects compared to the planner MOSFET because of better gate control mechanism. So, proposed Inverter would be efficacious to offer less power dissipation and higher speed. Impact of supply voltage and the temperature on the power and delay of the Inverter circuits have been detailed here. Extensive simulations have been done using SILVACO ATLAS to validate the proposed models. Besides, optimum, supply voltage has been proposed to enhance the efficiency at low supply voltage.