Contents I. Introduction
The continuous scaling of MOS structures generates short channel effects (SCEs) like corner effects, drain induced barrier lowering (DIBL), punch through, velocity saturation, threshold voltage roll-off and hot-carrier effect thereby degrading its overall performance [1]. In order to overcome these disadvantages, new MOS structures are being introduced and analyzed for different device parameters. The previously developed Multigate devices such as cylindrical Surrounding Gate (SG) and Double Gate (DG) MOSFET have overcome SCE to a great extent. These Surrounding Gate MOSFET helps in obtaining improved packing density, high driving current, and sharp subthreshold slope. It also reduces corner effect [2]–[3]. However, SG devices suffer from threshold voltage fluctuations, Drain Induced Barrier Lowering, and fabrication difficulties [1]. In conventional SG MOSFET, the silicon pillar is completely enclosed by the gate which helps in enhancing_gate controllability [4]. But here the issue with this device is the formation of abrupt S/D formation which increases the resistance of the device. The Double surrounding gate (DSG) MOSFET has two cylindrical gates, one on both the sides of the silicon film. DSG has high driving current and low leakage current. The inner gate provides a strengthened channel controllability. The self-alignment of the S and D regions to top as well as bottom gates, identically sized gates, and alignment of the two gates with each other prove as a disadvantage in case of DSG MOSFET [5]. This also leads to a reduced subthreshold leakage current
