Optimal eGaN?? FET Scaling for Minimal Power Loss in High Step-down Ratio Half Bridge Converters

The high-side (HS) and low-side (LS) FET losses in a high step-down ratio half bridge converter are dominated by switching loss and conduction loss respectively. As the design of a FET has to balance between switching and conduction loss related parameters, it opens up the possibility of optimizing HS and LS FET scaling for minimal total FET losses. This work analyzes the switching transition and loss mechanism of a hard-switched GaN FET, and experimentally evaluates HS and LS GaN FET scaling in a non-isolated 48 V to 5-12 V, 10 A DC/DC half bridge converter. It is seen that smaller FETs generate less loss in the low current range, and this range increases with frequency, while larger FETs outperform at high output current.