Device Design Consideration for Robust SiC VDMOSFET With Self-Aligned Channels Formed by Tilted Implantation

We designed a simple self-aligned process for defining short channels in 3.3-kV SiC mymargin DMOSFETs. We utilized a tilt-angle ion implantation technique in the process, and the channel region was formed with the same mask as the source definition. This process eliminates the complicated process of hard mask etching. The simulation showed that a channel is formed by implantation of ~1× 10
¹³
cm
²
and ≤600 keV, and channel length can be modulated by tuning incident angles and energies. When a separate mask is used for body formation, our proposed process is less sensitive to the alignment errors of the two masks. Variations in threshold voltages, ON-state resistance, and blocking voltages are significantly reduced in our process. We also show that the mask for body formation is not necessarily required, and we present a set of implantation parameters for channel and body formation only with the mask for the source.