DDJ-Adaptive SAR TDC-Based Timing Recovery for Multilevel Signaling

This paper describes a low-latency and low-power bimodal non-return-to-zero (NRZ) and pulse-amplitude modulation (PAM)-4 timing recovery circuit. This architecture reduces latency and power consumption by eliminating the need for data equalization in the timing recovery path in intersymbol interference (ISI)-limited channels. It directly equalizes data-dependent jitter (DDJ) by adaptively shifting the ISI-affected zero crossings. The implemented prototype in 65-nm CMOS supports both 10-Gb/s NRZ and 20-Gb/s PAM-4 while consuming only 23 mW. The clock and data recovery (CDR) achieves more than 20 MHz of peaking-free tracking bandwidth (BW) and adapts to optimized jitter tolerance for both PAM-4 and NRZ data eyes.