A Multiplexing DAPD Technique for Fast-Locking and Charge Pumps Calibration in PLLs

This letter presents a 5-GHz phase-locked loop (PLL) with fast-locking and charge pump (CP) calibration. Based on dual-mode time division multiplexing discriminator-aided phase detector (DAPD), the fast-locking and CP calibration procedure are proposed in a compatible and efficient manner. The proposed dual-mode time division multiplexing DAPD has coarse-resolution and fine-resolution modes, which is used in fast locking and CP calibration, respectively. The proposed technique is incorporated in a design of 5-GHz PLL. Implemented in the 0.18-μm 1P6M CMOS process, the power dissipation is less than 18.3 mW. The measured total settling time (including fast-locking and CP calibration) is 22 μs, evidently improved by 36 μs over the conventional method. At 4.905 GHz, the phase noise measured at 1-MHz offset is -123.7 dBc/Hz, and the measured output spur levels are less than -70.44 dBc throughout the whole output frequency range.