Hybrid Performance Modeling for Optimization of In-System-Structural-Test (ISST) Latency

In-System-Test (IST) is one of the most advanced feature of autonomous drive platforms to monitor the semiconductor chip failures due to field defects. This is achieved by application of structural-tests (Memory BIST and/or Logic BIST) during key-on and/or key-off functional events. The time duration for application of these structural tests, detection of defects, drive platform reaction, and leading it to a fail-safe state must be short enough to avoid hazards caused by defects in safety modules (SMs). The optimization of diagnostic test interval (test application and result analysis) is important to reduce the overall in-system-structural test latency. In this paper, we present the hybrid performance modeling methodology adopted for IST architecture to optimize the design implementation with lowest possible and acceptable diagnostic test latency for key-on and/or key-off application of structural-test in Drive platform.