Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests

We describe a novel methodology to validate path level static timing analysis (STA) on silicon by leveraging standard scan architecture and using hazard-free robust path delay tests. We have successfully validated a sizable set of timing paths on silicon across multiple advanced process nodes. Learnings from these STA correlation exercises on representative ASIC blocks in test chips have resulted in a silicon-proven STA signoff methodology with optimum guard-bands. The process health feedback has proved valuable for the process development team especially during the early development phase. We have observed that Fmax determined using hazard-free robust path tests is within ±5% of that using functional benchmark.