Influence of External Gate Resistance on UIS Capability in Superjunction MOSFET

We investigated the UIS capability for superjunction MOSFETs with respect to the external gate resistance (R
_g
) and the charge imbalance (CIB) by experiments as well as device simulations. Measured UIS capability depends not only on the CIB but also on the R
_g
. Higher UIS capability was exhibited for small R
_g
than for large R
_g
as deviating the CIB to while the difference by R
_g
was small for Qn=Qp. The device simulations indicated that the device destruction by UIS is assumed to be related to the re-conduction of channel current (I
_ch
). When the R
_g
is small, Ich turns off once while V
_ds
has not increased enough to generate impact ionization. This transient behavior is different from the one for large R
_g
. After that, Ich re-conduction occurs due to the high electric field beneath the MOS gate for Qn=Qp but suppressed for . The graded doping for N-column which reduces phosphorus concentration near the surface helps to suppress the re-conduction and improves the UIS capability for small R
_g
condition.