A Study of LDMOS BV Improvement by Gate Architecture Optimization

In this paper, various gate architectures of stepped gate oxide LDMOS are studied and multiple experiments are performed using two-dimensional TCAD simulation. It reveals that by using multi-gate structure with optimal underlying oxide thickness and field plate length, breakdown voltage (BV) can be greatly improved without sacrifice of specific on resistance (R
_sp
). The mechanism is that the optimal multi-gate structure has more uniform electric field distribution at the surface of device drift area.