A Background Timing Skew Calibration Technique in Time-Interleaved ADCs

This paper presents a background timing skew calibration technique for time-interleaved analog-to-digital converters(ADCs). The timing skew between two adjacent sub- ADCs is detected in the digital domain through slope-based and statistics-based technique. Based on the detection error, the digitally controlled delay line(DCDL) is driven to minimum the timing skew. Using the proposed calibration algorithm in a 14- bit 500MS/s TI ADC model, the MATLAB simulation result shows a convergence time of 346ms under Nyquist frequency input with 1% oTs initial timing mismatch, and the proposed method can effectively reduce hardware consumption in circuit implementation.