Performance Comparison of s-Si, In0.53Ga0.47As, Monolayer BP- and WS2-Based n-MOSFETs for Future Technology Nodes—Part II: Circuit-Level Comparison

The first part of this paper presented the device-level comparison of emerging materials (In_0.53Ga_0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In_0.53Ga_0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In_0.53Ga_0.47As FinFETs in sub-0.7-V supply voltage regime and In_0.53Ga_0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option.