A Comparative Analysis of Charge Pump Circuits for Improved Output Voltage Near Subthreshold Region

This paper aims at comparing the performance of different charge pumps used in low power IC design at various technology nodes. The performance degradation in the presence of inter-die and intra-die variations is supported by conducting PVT variations. To further analyse the effect of decreased channel length as one moves from 45nm towards 32nm region, process-corner analysis is carried out along with width and length variations and changing clock frequency on the same circuit. This paper aims to find the best charge pump circuit out of the chosen circuits. Simulation is carried out at 45nm and 32nm technology nodes. Results show that the Floating Well based charge pump provides around 71% increase in output voltage at 32nm technology node and an 80% increase at 45nm technology node, but as far as delay time is concerned, static CTS charge pump shows improved performance with a decrease of 79% at 32nm technology node and 81% for 45nm technology node, when compared to Dickson charge pump at an input voltage of 1V.