Transaction Based Speedup for Simulation Replay

In today's competitive world, RTL designers are tasked with implementing several new features and it becomes imperative for Verification Engineers to keep up with the validation of all the implemented features as well as the whole system. Any speedup added to the process of Testbench enhancement, achieved through the reduction in compute times, is always welcome. In this paper, we explain the process that we developed to accomplish this speed up by taking advantage of some simple software concepts and some tweaks in the verification infrastructure.