Multi-Master Validation Framework for Next Generation Automotive SOCs

In todays advanced System on Chip (SoCs), system interconnects and memories are the most common shared resources on which System and Intellectual Property (IP) performance depends heavily. In real applications, when these shared resources are used by multiple masters, deadlock or hang situation can occur in some specific scenarios e.g. the infamous Mars Pathfinder bus-lock issue. To avoid such situations, validating real-life use-cases during the silicon cycle becomes critical. Post-silicon validation being the last stage before Original Equipment Manufacturers (OEMs) start using the SoC in actual products, necessitates that multiple masters are run under emulated system traffic conditions similar to the targeted application use-case. This paper presents a novel methodology (Multi-master validation framework) to emulate real use-cases and run multiple masters in parallel using a Real Time Operating System (RTOS). The proposed framework will stress the system by running different subsystem settings defined by framework. The outcome of the test cases can be used to identify system performance bottleneck, optimal performance point or performance degradation of different masters (IPs) when run parallelly. This will also help in identifying critical bugs when shared resources are stressed which would not have been possible in standalone bare-metal IP tests, thus improving Total Quality of validation and Customer Quality Index (CQI).