A Gm/Id Based Methodology for Designing Common Source Amplifier

Device miniaturization is of great concern over past two decades which leads to further transistor size shrinking and improvement in their performance. As the transistor size is reduced there is a need to include short channel effects. These effects are not taken into consideration by conventional equation based amplifier design methodology. An alternative approach is to use graphical based Gm/Id technique. This methodology investigates the relationship between transconductance by drain current (Gm/Id) versus normalized drain current [Id/(W/L)] which is strongly related to the circuit performance. This result indicates the region of operation and also provides tool to calculate device dimensions by unified synthesis methodology in all regions of operation of a MOS transistor. In this paper, a common source amplifier with active load has been designed using Gm/Id technique to model the transistor size and meet the given design parameters such as GBW, gain and power consumption. Supply voltage of 1.8V is used here and a comparative analysis of these performance parameters is done for various technologies (180nm, 90nm, 45nm) using cadence virtuoso tool.