Improved Pareto Chart Analysis for Yield Detractors’ Identification

Nowadays integrated circuits (ICs) are produced in very fine technologies and include increasingly complex functions demanded by the new industry trends. This makes them even more sensitive to process variations than before. Variation is an expensive problem which can cause product delays, yield loss and redesign. Therefore, methods are needed for a quick and accurate IC yield analysis and failure root cause discovery in a cost- and time-efficient way. The paper introduces an improvement of the current Pareto chart analysis employed for yield detractors' identification using data-driven methods. This is achieved by performing clustering prior to the Pareto chart analysis. It proved to be a simpler method, which also leads to the identification of the yield detractors in reduced time compared to the classical Pareto chart analysis..