Hardware Acceleration of SHA-256 Algorithm Using NIOS-II Processor

Cryptography plays a leading role in the information transmission security. Even though encrypted, data can be altered when transmitted over a network. Therefore, to verify data the use of a digital signature is essential. Hashing algorithms are used both to create digital signatures and to verify the receiving data. Our proposed design of a Hashing algorithm, is a custom hardware implementation on a FPGA of the Secure Hash Algorithm-2 (SHA-2), using Nios II processor. We use two acceleration techniques, to improve performance of SHA-2 computation: floating point and floating point 2. Finally, after applying these techniques, we studied all the designs in terms of integration time, the number of clock cycles and the percentage of overlap in the FPGA.