Abstract:
In this paper, we propose the integration of a Ge-Sb-Se-N (GSSN) back-end selector with a HfO2/Ti resistive memory (RRAM) in 1S1R configuration. GSSN composition was tune...Show MoreMetadata
Abstract:
In this paper, we propose the integration of a Ge-Sb-Se-N (GSSN) back-end selector with a HfO2/Ti resistive memory (RRAM) in 1S1R configuration. GSSN composition was tuned in order to be optimized for RRAM characteristics, combining low leakage current without degrading operating voltages. Electrical characterization of 1S1R structure was achieved to quantify and extract device features. More than 2 decades were measured between ON and OFF states. Leakage current lower than 1nA was achieved on unselected devices (Vread/3). Modeling was performed in order to understand RRAM and OTS contributions in 1S1R conduction and to identify the best reading strategy. Based on 1S1R electrical performances, crossbar array was investigated predicting >1Mb size for the elementary array tile down to 10nm node.
Published in: 2019 IEEE 11th International Memory Workshop (IMW)
Date of Conference: 12-15 May 2019
Date Added to IEEE Xplore: 21 June 2019
ISBN Information: