Improvement of conduction in 3-D NAND memory devices by channel and junction optimization

We explore different ways to improve the quality of polysilicon channel in 3-D NAND flash devices to increase the current conduction. The analysis includes the formation of the device bottom junction (benchmarking diffused vs. epitaxially grown source), the role of defect passivation, the role of the protection layer on channel crystallization and the impact of macaroni channel thickness on grain size and on transistor performance.