Scaling Split-Gate Flash Memory Technology for Advanced MCU and Emerging Applications

In this paper, scaling prospects and challenges of embedded split-gate Superflash® (ESF) technology to 28 nm and below are discussed. The integration of the inherent HKMG in the select transistor of the split-gate memory cell ESF3 enhances the cell performance without compromising its reliability and results in lowering the embedded flash process cost. This result also paves the way for a conceptual ease of integrating ESF cell into a FinFET CMOS process node. This paper will also demonstrate the capability and performance of subthreshold current tuning of the 28 nm split-gate Superflash® cell and its potential implementation in analog computing applications.