High Throughput Implementation of SMS4 on FPGA

The SMS4 algorithm is a block cipher algorithm, which has the characteristics of high security and easy implementation. However, the optimization and implementation schemes proposed for FPGA platform currently use multi-channel parallel and pipelined architectures to improve performance, which results in a large consumption of resources, and the clock cycles taken to process a single data block is not reduced. This paper proposes a novel implementation scheme of SMS4 on FPGA. This scheme separates the generations of 32 round keys and encryption operations, 32 round keys are generated on the host computer in advance, and the encryption operations completed on the FPGA. At the same time, for the 32-round iterative structure of the SMS4, this paper proposes a dual-cascade implementation architecture that can compress 32 rounds of iterative operations from 32 clock cycles to 16 clock cycles. This greatly improves the performance of the SMS4. To compare with the previous works needing 32 cycles or more, which greatly reduces the clock cycles spent on processing each data block. The throughput achieves 1.9 Gbps at a frequency of 286 MHz on Xilinx FPGA.