Compressed bit fail maps for memory fail pattern classification

This paper presents a new approach to configure compressed bit fail maps to allow fail pattern recognition. Construction of the special compression scheme is shown. This takes typical memory array fail patterns into account. Examples for different failure types are given. This scheme allows minimizing the necessary cache memory size for fail classification. A 64 Mbit fail map can be compressed to 2 k allowing classification of 13 fail types. Since cache RAM requirements are small, this scheme can be implemented in a manufacturing environment for all processed hardware. Compressed bit fail maps can be used to generate wafer and lot maps for diagnosis.