Current testing procedure for deep submicron devices

This paper presents a test technique that employs two different supply voltages for the same I/sub DDQ/ pattern. The results of the two measurements are subtracted in order to eliminate the inherent subthreshold leakage. Summary of the experiment carried out on a "System on a Chip" (SOC) device build in 0.35 /spl mu/m technology is also shown. The experiments proved that the method is effective in detecting failures not detectable with the single limit I/sub DDQ/.