Comprehensive Performance Evaluation of Computationally Efficient Discrete Fourier Transforms for Frequency Estimation

In this paper, the design of frequency-locked loop (FLL) is proposed based on computationally efficient discrete Fourier transform (DFT) structures. In recent years, the DFT structures are evolved as sliding DFT (SDFT), modulated SDFT, hopping DFT (HDFT), modulated HDFT, and sliding-windowed infinite Fourier transform. Considering their tuned filter characteristics, an attempt has been made to obtain a solution for the instantaneous frequency estimation problem of the input signal under varying center frequency condition. In each DFT structure, the $k$ th bin in-phase and quadrature components are separated for instantaneous signal extraction. The feedback loop is designed around these DFT structures, and it was observed that the frequency responses exhibit flat magnitude and phase interestingly when compared with the open-loop structures. Hence, an adaptive sampling frequency adjustment scheme is proposed for these structures as FLL to estimate the instantaneous frequency of the input signal for the wide variation in center frequency. These FLLs with different DFT structures are tested for dynamic performance and wide operating range. The proposed FLLs are implemented in field-programmable gate array (FPGA), and the experimental investigations have been carried out for frequency estimation. Further experimental investigations on these FLLs as a system on chip were carried out with area and power analysis.