Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating

Power gating is commonly used to reduce leakage current in SRAM memories; leakage current has a large impact on SRAM energy consumption. We first focus on power gating FinFET SRAMs and then evaluate three techniques to reduce the leakage power and energy-delay product (EDP) of sixand eight-transistor (6T, 8T) FinFET SRAM cells. We compare the EDP savings obtained using: 1) power gating FinFETs; 2) near-threshold operation at V
_DD
= 0.6 V instead of the nominal VDD = 1 V; and 3) alternative SRAM cells with shorted gate (SG) and low power (LP) configured FinFETs; LP configuration reverse-biases a FinFET's back gate and reduces leakage current by up to 97%. SRAM cells with higher leakage benefit the most from power gating since they see the largest reductions in leakage current. Sharing power gating transistors among multiple SRAM cells can lead to more leakage current savings, but causes slower read and write speeds which can diminish their effectiveness. Alternative SRAM cells with lower leakage benefit the most from near-threshold operation to further reduce leakage current. Near-threshold operation and/or power gating reduces the 6T SG FinFET SRAM scheme's EDP slightly more than using the 8T SG FinFET SRAM scheme, but using an LP 8T SRAM scheme, such as LP_INV1.2, with near-threshold operation is more effective than power gating and provides the largest reductions in EDP. The design techniques recommended by this brief can enable longer battery life for small sensor systems and thus greater reliability for Internet-of-Things (IoT) devices.