LUT-Oriented Asynchronous Logic Design Based on Resubstitution

The method of asynchronous logic synthesis targeting area ((number of Look-Up-Tables -LUTs) minimization is proposed. Initially, a single-rail multi-level network is created using ABC synthesis system script. The improvement is done using the resubstitution. For the network compact representation and optimization, an extended PLA table is proposed. The resubstitution is formulated and solved as a covering task: the output of the node which input has been selected for the resubstitution is split into the set of dichotomies. The selected input is removed and the minimal number of inputs are sought to cover the dichotomies. Two-step procedure is proposed: 1) the resubstitution for a network produced by ABC is done; 2) the obtained network is transformed into dual-rail one and the resubstitution is done further. In each step, nodes with zero fan-outs are removed. The procedure guarantees indicating logic. The experiments show, that the result is more that 20% better w.r.t. number of nodes.